This application claims the priority of Korean Patent Application No. 2004-13570, filed on Feb. 27, 2004, in the Korean Intellectual Property Office, the disclosure of which is herein incorporated entirety by reference in its entirety.
1. Field of the Invention
The present invention relates to an interrupt controller, for example, an interrupt controller which may allocate interrupt source signals. The interrupt controller may perform priority based allocation of interrupt source signals received concurrently by the interrupt controller.
2. Description of the Related Art
A microprocessor may have an interrupt controller used for processing interrupt source signals. If a plurality of interrupt source signals are generated concurrently, then a priority may be assigned to each of the interrupt source signals to determine which of the interrupt source signals to process first.
To determine priorities for interrupt source signals, a register may be used to set bits, for example, bits which identify interrupt source signals generated by a plurality of modules. Priorities for interrupt source signals may be determined based on bits set in the register.
FIG. 1 is a block diagram illustrating an example structure of a conventional interrupt controller. Referring to FIG. 1, the interrupt controller 100 may include, for example, an interrupt pending register 10, a control register 20, a priority register 30, and an interrupt request signal generator 40. Also, a central processing unit (CPU) 50 may be included in the block diagram of FIG. 1 for explanation purposes related to the operation of the interrupt controller 100.
An example operation of the block diagram illustrated in FIG. 1 may include inputting an interrupt source signal (IS) to the interrupt pending register 10. The interrupt pending register 10 may include a register that manages interrupt source signals having different priority levels. For example, if two or more interrupt source signals are generated concurrently, then the interrupt pending register 10 may give priority to the interrupt source signal having the highest assigned priority. Determining the priority of the interrupt source signals may include referencing bits set in a register to identify the priority levels of the interrupt source signals.
The control register 20 of FIG. 1 may perform one or more control operations. Performing a control operation may include, for example, determining whether to perform a mask operation to mask an input interrupt source signal (IS) and/or to support a vector function for the interrupt controller 100. The control register 20 may transmit interrupt source signals to the priority register 30 that correspond to one or more sets of bits of the interrupt pending register 10.
The priority register 30 of FIG. 1 may include a logic circuit which determines the priorities of the interrupt source signals by using a fixed technique or a round-robin technique. The interrupt source signals may be located in a master block, which may divide the input interrupt source signals into one or more groups and control the individual groups.
The interrupt request signal generator 40 of FIG. 1 may generate an interrupt request signal (IRQ) in response to one or more interrupt source signals received from the output of the priority register 30. If CPU 50, for example, receives the interrupt request signal (IRQ) from request signal generator 40, then the CPU 50 may identify which interrupt source signal has been generated. FIG. 2 is a schematic diagram illustrating the structure of a conventional priority register 30 of FIG. 1. Referring to FIG. 2, the priority register 30 may include, for example, five registers (REG1˜REG5). It may be assumed for example purposes, that the interrupt controller 100 of FIG. 1 has a 32-bit bus capable of performing 32 interrupt signal operations at a time.
An example operation of FIG. 2 may include the first through the fourth registers (REG1˜REG4) each receiving eight corresponding interrupt source signals (IS1˜IS7, IS8˜IS16, IS17˜IS24 and IS25˜IS32), and determining priorities for each of the four sets of eight interrupt source signals. The four registers (REG1˜REG4) may each output an interrupt source signal having a highest priority to the fifth register (REG5) once the priorities of the interrupt source signals have been determined. The fifth register (REG5) may receive the highest priority signals from the four registers (REG1˜REG4), and the fifth register (REG5) may output an interrupt source signal having the highest priority among the signals received.
A frequently generated interrupt source signal may be given a higher priority for faster processing, which may increase the performance of an interrupt controller and/or a system having an interrupt controller. Interrupt source signals with low priorities may be processed infrequently or not at all, depending on whether an interrupt source signal with a higher priority is generated too frequently. If, for example, interrupt source signals that have a lower priority are not processed, the system operation may be dysfunctional. As the number of interrupt source signals increases, determining the priority level of the interrupt source signals may help to increase the performance of the interrupt controller 100.
The interrupt controller 100, according to an example embodiment of the present invention, may be designed to adjust the priorities of interrupt source signals. The interrupt source signals may be divided into separate groups, as shown in FIG. 2. The priorities of interrupt source signals may be adjusted based on the assigned groups and/or the priorities may be further adjusted among the interrupt source signals within each group. Example techniques that may be used for determining the priorities of interrupt source signals may include a fixed and/or a round-robin technique.
The fixed technique may be used to determine priorities for groups based on a set of priorities, however, the fixed technique may overlook lower priority interrupt source signals. For example, an interrupt source signal of a higher priority group may be generated more frequently than an interrupt source signal of a lower priority group. If a user desires to input an interrupt source signal, the fixed technique may not permit the interrupt source signal to be moved independently of its respective group to a different register. Referring to FIG. 2, a user may desire to move an input signal, for example IS25 of REG4, to the first register REG1 to allow the interrupt source signal IS25 to be processed faster. Using the fixed technique, the user may not be able to move the interrupt source signal IS25 to the first register REG1 without also moving all of the interrupt source signals IS25˜IS32 of the fourth register REG4. The fixed technique may not permit a user to freely control the order that interrupt source signals are handled by the interrupt controller 100.
The round-robin technique may assign the interrupt source signals with priorities that are not fixed. An example of round-robin may include assigning a lowest priority to the first interrupt source signal processed, and assigning a highest priority to the interrupt source signal with the next highest priority. However, changing the priority of an interrupt source signal may not be easily accomplished, for example, in a real-time system, it may be difficult to predict the order the interrupt source signals will be processed.
The interrupt controller 100 of FIG. 1 may be operating in a 32-bit bus system. The interrupt controller 100 may include one or more registers suitable for handling 32 bits. A 32-bit register may provide allocation for 32 interrupt source signals, however, interrupt source signal generated in excess of 32 may not be processed.